1. Field of the Invention
The present invention relates to an all-digital phase-locked loop, and more particularly, to an all-digital phase-locked loop in a frequency synthesizer.
2. Description of the Prior Art
Phase-locked loop (PLL) can be used for clock/data recovery, frequency or phase modulation/demodulation, and generating clocks having stable frequency. In general, a conventional PLL is usually implemented as an analog PLL that comprises a phase frequency detector (PFD) for detecting phase and frequency of signals and a loop filter for adjusting the operation of a VCO according to the detection result of the PFD.
Passive components of an analog PLL are easily affected by noise such that undesirable effects may be caused. Therefore, it is more and more popular to utilize digital architecture to implement PLLs. Additionally, processing digital signals is often easier than processing analog signals. However, some components of a conventional digital PLL, such as a digital loop filter and a digital controlled oscillator (DCO), requires an external high frequency signal as the working clock. This requirement not only increases the implementation cost but also limits the performance of the system using the conventional digital PLL due to the source of the external high frequency signal.